In order to build faster and more complex integrated circuits, semiconductor device manufacturers have increased the number of components in to the integrated circuits, while reducing the overall size of the circuit. The small circuit size requires multiple overlying metal interconnect layers to electrically connect the vast number of components within the integrated circuit. The multi-level metal interconnects are necessary in order to provide the large quantity of electrical connections necessary to electrically couple the large number of device components to each other, and to electrical circuitry within device packaging.
With the advent of very-large-scale-integration (VLSI) semiconductor technology, multi-level interconnect layers must be fabricated at high density levels. Each metal interconnect layer includes a large number of metal leads arrayed over an interlevel dielectric layer. The individual metal leads are fabricated using high resolution photolithographic and etching methods to have a very small line width. A high packing density of metal leads is obtained by placing the leads very close together, such that a very small line-space pitch is achieved.
In addition to multiple layers of metal, VLSI semiconductor devices also include passivation materials overlying the interconnect layers to protect the underlying circuitry from contamination and from physical damage. Most commonly, multiple passivation layers are employed to relieve stress in the underlying metal and dielectric layers. Excessive stress can cause cracking and void formation in the interconnects resulting in the loss of electrical signals from the affected components within the device. The passivation materials are typically silicon oxides and silicon nitrides. Passivation materials, such as silicon nitride, are commonly used to prevent mobile ions from entering the device structures and causing problems, such as threshold voltage shifting in metal-oxide-semiconductor (MOS) transistors within the device.
As successive layers of conductors and dielectric materials are deposited over previously defined structures, the surface topography can become extremely uneven. The surface roughness is substantially increased when multi-level metal interconnects are used. Also, the requirement for high-density interconnects in VLSI devices further exacerbates the uneven surface topography upon which the passivation layers must be applied. At some point, the surface topography become so uneven that the passivation layers cannot uniformly coat the underlying interconnects. When this happens, voids and open spaces can be created below the passivation layers.
The creation of open spaces within the device is problematic because gases, such as water vapor, can easily collect within the open spaces. In the case of water vapor, water can condense within the open spaces and cause corrosion within the interconnect layers. Most VLSI devices employ a large number of metals, such as copper, copper-aluminum alloy, and the like, which are subject to corrosion upon contact with water. Additionally, gas pressure can build up within the spaces and cause a phenomenon known as "popcorn" cracking in package devices. When this occurs, high pressure gases literally explode out of the package damaging circuit elements in the process. Even in the rare case where a circuit element is not damaged, a leakage path for moisture is created as the outrushing gases create cracks in the various dielectric layers within the package. Once the cracks have been formed, the both moisture and mobile ions can penetrate the passivation layers and contaminate the underlying device components resulting in catastrophic device failure. Accordingly, a need existed for an improved passivation material and process to eliminate the formation of voids and open spaces at the passivation/interconnect interface.